Fixed Gate Bias of Depletion MOSFET

Depletion MOSFET can be biased using either zero bias, fixed gate bias, self bias, drain feedback bias, voltage divider bias, two supply bias or current source bias. These types of mosfet biasing methods are the same as for JFET biasing methods except that with depletion MOSFET we have additional bias method called zero gate bias. Depletion type MOSFET can be used either in depletion mode and enhancement mode. In depletion mode the gate to source voltage is biased so that it is negative and in enhancement mode the gate to source is biased so that it is positive. Hence in using fixed gate bias for depletion MOSFET we can make the gate to source voltage either positive or negative. This is unlike in JFET which works only in depletion mode and hence the gate the source voltage must be kept negative(reverse biasing the gate to source junction). Here fixed gate bias or fixed bias of depletion MOSFET is illustrated. We will use LND150 depletion MOSFET transistor.

Contents

1. Fixed Gate Bias of Depletion MOSFET in Enhancement Mode
2. Fixed Gate Bias of Depletion MOSFET in Depletion Mode
3.  Recommended Tutorials

Fixed Gate Bias of Depletion MOSFET in Enhancement Mode

The following shows the circuit diagram of fixed gate biased depletion MOSFET in enhancement mode.

In fixed gate bias, a fixed gate voltage is applied to the gate of the FET. This is enhancement mode circuit because the gate voltage applied $V_G$ is positive. The drain resistor $R_D$ is used to control the drain current $I_D$ and the drain to source voltage $V_{DS}$. 

This circuit can be biased according to the application which can be either variable resistor, switching or amplification. 

Voltage controlled Resistor

Consider that we want to use it as a voltage controlled variable resistor. Then we need to bias the circuit in the ohmic region. To bias it in the ohmic region we need to locate the operating point or the Q-point in the ohmic region. Following shows the drain curve characteristics of LND150 transistor along with the ohmic region and the selected Q-point of operation.

The supplied voltage $V_{DD}$ is used in this example. From the graph, the selected Q-point is,

$V_{DSQ}$ = 1.75V,  $I_{DQ}$ = 3.14mA with $V_{GS}$ = 600mV(enhancement mode).

The load line intersects the drain axis at,

$R_D=\frac{V_{DD}}{I_{DL}}$

From the graph, $I_{DL}=4.75mA$ and therefore,

or, $R_D=\frac{5V}{4.75mA}$

that is, $R_D=1k\Omega$

So the completed fixed gate biased circuit of enhancement mode depletion type MOSFET is shown below.

 

Now if a variable dc voltage is applied to the gate then the resistance of the MOSFET transistor changes. If the applied dc voltage increases the resistance decreases and vice versa. So in this way the fixed gate biased depletion type MOSFET can be used as a variable resistor controlled by input voltage. 

Amplifier

Enhancement mode Depletion MOSFET biased in Ohmic region

FET amplifier are usually biased in the linear region or the active region. But because the depletion type MOSFET can be biased either by positive and negative gate to source voltage, it can work as an amplifier in the ohmic region. Hence the same above fixed gate biased depletion MOSFET in enhancement mode can work as an amplifier.

 

Input/Output Impedance & Coupling capacitors 

The calculation of the coupling capacitor requires ac analysis. The calculation of the coupling capacitor is as follows.

The approximate input impedance of a fixed bias is,

$Z_i \simeq R_G =1M\Omega$

And the input coupling capacitor value at the frequency of 1KHz is,

$C_1 = \frac{1}{2 \pi f (0.1) Z_i}$ 

which gives, $C_1 \simeq 1.6nF$ 

The approximate output impedance of a fixed bias is,

$Z_i \simeq R_D = 1k\Omega$

And the output coupling capacitor value is at the frequency of 1KHz

$C_2 = \frac{1}{2 \pi f (0.1) Z_i}$ 

which gives, $C_2 \simeq 1.6\mu F$ 

Voltage Gain

 The gain of the fixed biased FET can be derived to be approximately as follows,

$A_v = - g_m R_D$

where $g_m$ is the transconductance of the FET and its value is calculate using the following formula,

$g_m=\frac{2 I_{DSS}}{|V_P|}(1- \frac{V_{GSQ}}{V_P})$

From the drain graph above we have,

$V_P=-2V$, $I_{DSS}=2.33mA$ and $V_{GSQ}=0.6V$

therefore, $g_m=\frac{2 (2.33mA)}{2}(1- \frac{0.6}{-2})$

that is, $g_m\simeq3mS$ 

Hence the voltage gain is,

$A_v = - (3mS)(1k\Omega)$

that is  $A_v = - 3$

The following shows the simulated waveform of input signal of  on oscilloscope.

Enhancement mode Depletion MOSFET biased in linear region

FET amplifier when used as an amplifier as biased in the linear region. Here we will bias the enhancement mode fixed biased depletion MOSFET in the linear region for constructing an amplifier. The Q-point selected in the 

From the graph, the selected Q-point is at,

$V_{DSQ}$ = 4V,  $I_{DQ}$ = 3.5mA with $V_{GS}$ = 600mV(enhancement mode).

The load line intersects the drain axis at,

$R_D=\frac{V_{DD}}{I_{DL}}$

From the graph, $I_{DL}=18.3mA$ and therefore,

or, $R_D=\frac{5V}{18.3mA}$

that is, $R_D \simeq 273\Omega$

The drain to source voltage $V_{DS}$ is,

$V_{DS}=V_{DD}- I_D R_D$ 

or, $V_{DS}=5V- (3.5mA)(273\Omega)$ 

that is $V_{DS}\simeq4V$

The circuit diagram of depletion MOSFET in enhancement mode with fixed bias in linear region is shown below.

Input/Output Impedance & Coupling capacitors 

The calculation of the coupling capacitor is as follows.

The approximate input impedance of a fixed bias is,

$Z_i \simeq R_G =1M\Omega$

And the input coupling capacitor value at the frequency of 1KHz is,

$C_1 = \frac{1}{2 \pi f (0.1) Z_i}$ 

which gives, $C_1 \simeq 1.6nF$ 

The approximate output impedance of a fixed bias is,

$Z_i \simeq R_D = 273\Omega$

And the output coupling capacitor value is at the frequency of 1KHz

$C_2 = \frac{1}{2 \pi f (0.1) Z_i}$ 

which gives, $C_2 \simeq 5.8\mu F$ 

Voltage Gain

 The gain of the fixed biased FET can be derived to be approximately as follows,

$A_v = - g_m R_D$

where $g_m$ is the transconductance of the FET and its value is calculate using the following formula,

$g_m=\frac{2 I_{DSS}}{|V_P|}(1- \frac{V_{GSQ}}{V_P})$

From the drain graph above we have,

$V_P=-2V$, $I_{DSS}=2.33mA$ and $V_{GSQ}=0.6V$

therefore, $g_m=\frac{2 (2.33mA)}{2}(1- \frac{0.6}{-2})$

that is, $g_m\simeq3mS$ 

Hence the voltage gain is,

$A_v = - (3mS)(273\Omega)$

that is  $A_v \simeq - 0.82$

Fixed Gate Bias of Depletion MOSFET in Depletion Mode

In depletion mode, the gate to source voltage is negative. That is the gate to source junction is reversed biased. The circuit diagram of fixed gate bias of depletion MOSFET in depletion mode. 

In the above circuit the gate to source junction is reversed by the gate voltage supply which is $V_G$=-600mV. We can bias this circuit either in the ohmic region or linear region depending upon the application required.

Voltage Controlled Resistor

One of the application of MOSFET is as a voltage controlled resistor. When designing a MOSFET as a voltage controlled resistor it is biased in the ohmic region. In this we select the biasing point or the operating point in the ohmic region and find out the drain current and drain to source voltage required. From knowing the drain current and drain to source voltage we can then calculate the drain resistor value. 

The following shows selection of Q-point in the ohmic region. 

From the graph, the selected Q-point is at,

$V_{DSQ}$ = 750mV,  $I_{DQ}$ = 920uA with $V_{GS}$ = -600mV(depletion mode).

The load line intersects the drain axis at,

$R_D=\frac{V_{DD}}{I_{DL}}$

From the graph, $I_{DL}=1.25mA$ and therefore,

or, $R_D=\frac{5V}{1.25mA}$

that is, $R_D \simeq 4 k\Omega$

The drain to source voltage $V_{DS}$ is,

$V_{DS}=V_{DD}- I_D R_D$ 

or, $V_{DS}=5V- (920uA)(4 k\Omega)$ 

that is $V_{DS}\simeq 1.32V$ 

 Recommended Tutorials

- How to design JFET source follower?

- How to design Common Gate JFET Amplifier