How to design Common Gate JFET Amplifier

JFET(Junction Field Effect Transistor) can be used in three different topology- common source JFET amplifier which is most commonly used, common drain JFET amplifier which is also known as source follower and common gate JFET amplifier. Here it is explained how to design common gate JFET amplifier with worked out example.

The following shows the circuit diagram of a JFET amplifier with common gate configuration.

The input signal(V1) is applied to source and the output is taken from the drain. The gate is grounded and hence the circuit is called common gate configuration. In this common gate amplifier example, let us consider that the JFET is N channel 2N5459 JFET. Also we will use power supply voltage of $V_{DD}=+5V$ and $V_{SS}=-5V$. That is we are using JFET with two-supply source bias in this amplifier design. We will also suppose that the load resistor $R_L=10 k\Omega$.

To use the JFET transistor as an amplifier we need to bias the transistor such the operating point is in the middle of the transconductance curve. Doing this gives maximum possible swing for the output drain current $I_D$ for gate to source voltage input $V_{GS}$. The drain current is controlled by the applied gate to source voltage as indicated by the Shockley equation for JFET. 

So the first step in the design of JFET amplifier is to first establish a stable operating or Q-point for the JFET. For this we will set the gate to source voltage at the midpoint between 0V and the pinch off voltage $V_P$. Once we have set the gate to source voltage we then calculate the drain current $I_D$. After knowing the drain current we can then calculate the resistor values for drain resistor $R_D$ and source resistor $R_S$.

Contents

1. Determining gate to source voltage $V_{GS}$ 
2.  Determining drain current $I_D$
3. Determining source resistor $R_S$ 
4. Determining drain resistor $R_D$ 
5. Calculating coupling capacitors values
6. Simulation and Results

Determining gate to source voltage $V_{GS}$ 

The following shows how selecting the gate to source voltage between 0V and $V_P$ gives maximum possible swing for the output drain current $I_D$. In this case, the drain current can swing from 0 to $I_{DSS}$.

 

The value of $V_P=V_{GS(off)}$ can be found in the JFET datasheet or by graphically plotting the drain curve. Here we will use the Proteus Software to plot the drain curve. The tutorial Import spice model in Proteus and draw JFET drain curve shows how to plot the transfer characteristics in Proteus Software. Below is the drain curve graph for 2N5459 in proteus.

From the graph the value of $V_P=V_{GS(off)}$ is 1.2V. For the reason explained above we will bias the JFET with gate to source voltage as follows,

$V_{GS}=\frac{V_P}{2}=\frac{-V_{GS(off)}}{2}=\frac{-1.2V}{2}=-0.6V$

 Determining drain current $I_D$

Next we need to determine the drain current$I_D$ for gate to source voltage of -0.6V. We can determine the drain current for given gate to source voltage either using Shockley equation or using the drain graph above. The transconductance equation or the Shockley equation is as follows,

$I_D=I_{DSS}(1-\frac{V_{GS}}{V_P})^2$ 

But here we will use the drain current value for $V_{GS}=-0.6V$ from the graph instead of using Shockley equation because the spice model for 2N5459 in Proteus turns out to be different from the datasheet. From the drain graph when $V_{GS}=-0.6V$, drain current is $I_D=1.6mA$. Now we can proceed to calculate the source and the drain resistor values.

Determining source resistor $R_S$ 

For calculating the source resistor \R_S\) value we use the following equation,

$V_{GS} - I_D R_S - V_{SS} = 0$

and therefore,

$R_S = \frac{V_{SS}-V_{GS}}{I_D}$

that is,  $R_S = \frac{5-(-0.6V)}{1.6mA}=3.5 k\Omega$

Determining drain resistor $R_D$ 

For calculating the drain resistor $R_D$ we use the following equation,

 $V_{DD} = I_D R_D - V_D$

or, $R_D = \frac{V_{DD}-V_D}{I_D}$

Let us set the drain voltage $V_D = 2.5V$, then

$R_D = \frac{5V-2.5V}{1.6mA}$

that is,  $R_D = 1.56k\Omega$

Calculating coupling capacitors values

Finally we have to calculate the coupling capacitors values. Let the frequency of the input signal be 1KHz for this common gate amplifier example.

To calculate the input coupling capacitor $C_{c1}$ we need to find out the input impedance $Z_{in}$. The input impedance is,

$Z_{in}= R_S$

that is,

$Z_{in} = 3.5 k\Omega$

And the input coupling capacitor $C_{c1}$ is,

$C_{c1}=\frac{1}{2 \pi (f) (0.1) (Z_{in})}$

This formula is explained in the tutorial How to bias a BJT using voltage divider biasing.

 $C_{c1}=\frac{1}{2 \pi (1kHz) (0.1) (3.5 k\Omega)} = 0.45 \mu F$

The output coupling capacitor is calculated using the formula,

 $C_{c2}=\frac{1}{2 \pi (f) (0.1) (Z_{out})}$

where the output impedance is,

 $Z_{out}= R_D$

Hence,

 $C_{c2}=\frac{1}{2 \pi (f) (0.1) (R_D)}= \frac{1}{2 \pi (1 kHz) (0.1) (1.56 k\Omega)}$

that is,   $C_{c2}=1 \mu F$

How these coupling capacitor formula are derived is explained in details in the tutorial How to bias a BJT using voltage divider biasing.

Simulation and Results

The following shows the circuit diagram of common gate JFET amplifier with calculated resistors and coupling capacitors values.

The following shows simulation result of voltages and current of the above designed common gate amplifier circuit diagram.

An input signal of amplitude 100mV and frequency of 1kHz is applied to the source via the coupling capacitor Cc1. The input signal waveform and the amplified output signal waveform from the common gate JFET amplifier on a oscilloscope is shown below.

This shows that the output signal is amplified and out of phase with respect to the input signal in common gate configuration. 

So in this tutorial we explained with worked out calculation how to design Common Gate JFET Amplifier.